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Verilog_and_VHDL_Tools
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Accolade Design Automation, Inc. - Offering advanced tools for FPGA and system-level design using VHDL.
 
Aldec - HDL design entry and simulation software for programmable logic designers.
 
Avant! Corporation - Develops, markets, and supports integrated circuit design automation software for the physical design of high-density, high-performance integrated circuits. (Nasdaq: AVNT)
 
C Level Design - Offers a design and verification environment for C/C++ with synthesis to VHDL and Verilog code.
 
CAST, Inc. - Tools for intellectual property (IP) management. Plus synthesizable cores and simulation models using VHDL and Verilog.
 
Calyptech Design Services - Offers ASIC and FPGA design and verification services, drivers and tools. Includes product and service overview and PDF detailed product specifications available.
 
Cypress Warp Tools - VHDL and Verilog tools for use with the Cypress CPLD family.
 
Doulus - Lots of VHDL and Verilog resources. Including PaceMaker Self-Teach software.
 
Esperan - VHDL, Verilog and FPGA training courses held in the US, Europe and the UK.
 
Exemplar
 
Experimental Computing Laboratory - Includes papers, presentations, conference publications and SAVANT VHDL, a free VHDL analyser and simulator. From University of Cincinnati.
 
Freeware Verilog & VHDL - This is the home page for a Freeware Verilog,VHDL and Analog Mixed Signal project (a.k.a. the V-2000 project, still in its infancy).
 
Green Mountain Computing Systems - A software development company started in 1994, specializing in language systems. We currently develop and market tools for VHDL, an IEEE standard language for hardware description.
 
Hamburg VHDL Archive - Home of many free, open source designs in VHDL.
 
Nova Engineering - Megafunctions are modular, DSP algorithms and functional blocks for custom use in PLD or ASIC designs.
 
Rajesh Bawankule's Verilog Center - Verilog Center is an Oracle of Verilog Hardware Description Language and E.D.A. May you find answers to all your questions.
 
Sandstrom Engineering - HDL pre-synthesis tools which check code for synthesizability. Then suggest replacement code where problems are found.
 
Saros - Offering a full suite of VHDL and Verilog design tools, from design-entry, simulation and synthesis to verification and training.
 
StateCAD - Automatic VHDL and Verilog code from graphical state machine and data flow logic.
 
 
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